The present invention relates generally to an integrated memory device, an integrated memory chip and a method for fabricating an integrated memory device, and, in one embodiment, to a novel structure for a UCP (Uniform Channel Program) flash memory device.
Currently integrated memory device design, memory chip design and integrated memory circuit design are shaped by the continuous trend toward a higher storage density and toward higher write and read speeds while maintaining energy consumption of the memory devices and memory chips at a reasonable level.
Innovations in this field have been made to a greater extent in the area of the respective semiconductor technology used to fabricate such memory chips, but have related less to the basic structure of the known standard memory device.
In the following for the sake of brevity integrated memory device and integrated memory chip are shortly referred to as memory devices and memory chips.
UCP flash memory devices typically use Fowler-Nordheim tunneling for both read and write operations on a floating gate. In case of the customary basic structure of an UCP flash memory device, the stored digital information is retained by charged storage on the floating gate of the UCP flash memory device.
Typically the floating gate of such a memory device is assigned to a wordline WL via a (conventional, connected) selection gate of the memory device.
Setting the level of a wordline WL, i.e. of the selection gates of the corresponding integrated memory devices to low, causes these memory devices to be deselected for write and read operations.
If, in the case when a memory device is selected, this selected memory device, the floating gate of which is occupied by a stored charge representing a high level, is read out, a static read current flows through the channel formed between its drain terminal and its source terminal.
Upon read-out of a selected memory device the floating gate of which is occupied by a stored charge representing a low level, however, the channel is not sufficiently formed between its drain terminal and its source terminal and hence no or only a small static read current flows between the terminals.
In the known devices, the read-out of a selected memory device within a set of memory devices arranged in a plurality of memory device columns corresponding to bitlines is affected by connecting the source terminals and the drain terminals of the memory devices in each memory device column respectively in parallel to two separate respective bitlines per memory device column.
By using contact-connections the two bitlines can be set to predetermined potentials. In contrast to other memory device concepts in which the bitlines connected to the source terminals of the memory devices (i.e. the source lines) of different memory device columns can be set to a common potential, this is not possible in the case of the standard UCP flash memory device concept.
Hence a resulting static read current flows on the two respective bitlines connected to the memory device selected within a memory device column by the wordline. The magnitude of the occurring static read current represents the logic level of the memory occupancy of the selected memory device within a memory device column.
Moreover it is apparent from the above that two bitlines (for drain and source terminals) are necessary for memory devices according to the prior art for the read-out of the memory occupancy of prior art UCP flash memory devices.
Thus known memory devices are limited in the direction of the wordline in terms of its minimum dimensions to twice the conductor spacing requirements of the used semiconductor process (e.g., Infineon's C9FLR2-UCP, C120FL and C11FL/A technologies). In case of e.g., 1T UCP flash memory device the memory device pitch is limited to twice the minimum pitch of metal 2 and metal 3. As a result the limiting of the bitline pitch by the conductor pitch currently leads to relatively large sized memory device areas of 1T UCP memory devices.
Routing the bitlines in different wiring planes does not help to overcome the spacing limitations since, in principle, the spacing requirements between the interconnects and the contact holes (vias) for connecting different wiring planes in general are of the same magnitude as the spacing requirements between two interconnects.
Correspondingly the method to place the metal layers used for the bitlines one above the other is unsuitable for reducing the size of the device. One of the reasons for this is that the design rules for the stacked vias demonstrated that they necessitate substantially narrower tolerances than the design rules for metal layers lying one next to the other.
Due to the associated lower yield that is to be expected in this case, it is rather unlikely that the space saving would be successful.
Parallel to the bitlines, the memory device pitch dimension is typically already configured in minimal fashion corresponding to the state of the art. Thus the current concepts for UCP memories use particularly aggressive interconnection design rules in order to enable memory cell sizes that are as small as possible. In addition, the critical situation in the design of the memory cell is increased if the required contact-connections are realized in order to apply the necessary potentials to the two bitlines.
Correspondingly a competitive disadvantage remains for standard UCP memory devices in comparison with other device concepts, particularly in the case of large and very large memories.
For these or other reasons, there is a need for the present invention.